Method for patterning sub-lithographic features in semiconductor manufacturing

ABSTRACT

A method of forming a gate electrode ( 24 ′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer ( 26 ), for example formed of silicon-rich nitride, is deposited over a polysilicon layer ( 24 ) from which the gate electrode ( 24 ′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer ( 29 ) is then formed over the hardmask layer ( 26 ), and photoresist ( 30 ) is photolithographically patterned to define the pattern of the gate electrode ( 24 ′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist ( 30 ) to the BARC layer ( 29 ). The remaining elements of the BARC layer ( 29 ) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer ( 26 ) by an anisotropic etch of that layer, using the trimmed BARC elements ( 29 ) as a mask. The hardmask layer elements ( 26 ′) then mask the etch of the underlying polysilicon layer ( 24 ), to define the gate electrodes ( 24 ′), having gate widths that are narrower than the minimum dimension available through photolithography.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

BACKGROUND OF THE INVENTION

This invention is in the field of semiconductor integrated circuitmanufacturing, and is more specifically directed to thephotolithographic patterning and etch of device features.

In the field of integrated circuit manufacturing, a fundamental goal todesign and manufacture integrated circuits to be as small as possible.As is well known in this art, the manufacturing cost of an integratedcircuit corresponds strongly to the wafer area occupied by eachintegrated circuit die or chip. This is because the chip area correlatesdirectly to the number of possible integrated circuits per manufacturedwafer, and because the theoretical yield, for a given manufacturingdefect density, increases as chip area decreases. In addition, smallerfeature sizes result in improved device performance and increasedfunctionality for a given chip area.

In the manufacture of metal-oxide-semiconductor (MOS) integratedcircuits, the gate electrode is typically the physical feature that isthe smallest feature defined by a photolithographic pattern. Asfundamental in the art, the size of the gate electrode in turn definesthe MOS transistor channel length, which is an important physicalparameter in defining both the device density and also the transistorperformance in an MOS integrated circuit. Indeed, specific processingtechnologies are typically referred to by the nominal transistor channellength. And in turn, the transistor gate electrode width is oftenreferred to as a “critical dimension” or “CD” feature of the integratedcircuit.

Conventional photolithography processes are used to form integratedcircuit features. As is fundamental in the art, photolithographyinvolves the exposure to light of a photosensitive material, typically aphotosensitive polymer film referred to as photoresist, that isdispensed over the material that is to be selectively etched in formingthe integrated circuit at the surface of a semiconductor substrate(typically a semiconductor wafer). After exposure of the photoresist tolight, through a photomask or reticle, and subsequent developing,selected portions of the photoresist film are removed to leavecross-linked photoresist structures in a pattern corresponding to thepattern of the photomask. The remaining photoresist pattern defines thelocations of the underlying material that are to be protected from asubsequent etch, in turn defining the locations of the integratedcircuit structures to be formed from that material. In some cases, thephotoresist masks the etch of an insulating material that itself becomesa mask (i.e., a “hard” mask) of the etch of another layer underlyingthat insulating material. Either through the action of the etch itself,or a subsequent cleanup or ash, any remaining photoresist is removedfrom the wafer prior to the next deposition or other manufacturingprocess.

In recent years, the “critical dimension” of MOS transistor gate widthshas become significantly smaller than 500 nm. These small dimensionshave been attained using photolithography, despite the recurringpredictions that photolithography is limited in the feature sizes thatit can define. These predictions have proven false because of importantadvances in the field, including the use of ever-shorter wavelengths oflight, the use of more complex photomasks (e.g., phase-shiftphotomasks), anti-reflective coatings, and the like.

In addition, certain etch techniques are used to form features that areeven smaller than those that can be photolithographically defined, suchfeatures sometimes referred to as “sub-lithographic” features. Theseconventional processes typically involve post-development blanketreduction of the size of the masking features. FIGS. 1 a through 1 dillustrate, in cross-section, an example of such a conventional process,for the typical example of forming a sub-lithographic polysilicon gateelectrode.

FIG. 1 a illustrates substrate 2, and overlying gate dielectric layer 3.Polysilicon layer 4 overlies gate dielectric layer 3, and is the layerthat will be patterned and etched according to this conventionalphotolithographic process. In this example, a two-layer hardmask will bein place during the polysilicon etch. Silicon-rich silicon nitride layer6 overlies polysilicon layer 4, and silicon-oxynitride layer 8 overliessilicon-rich nitride layer 6. The relative thicknesses of silicon-richnitride layer 6 and silicon-oxynitride layer 8 are selected, in thisconventional example, to minimize reflections of the light in thephotolithographic exposure. As is also shown in FIG. 1 a, photoresist 10overlies a portion of silicon oxynitride layer 8, at a locationcorresponding to the location of the eventual gate electrode to beformed in polysilicon layer 4. At the stage shown in FIG. 1 a,photoresist 10 has been exposed to masked electromagnetic energy(typically of a wavelength in the so-called “deep UV” range), and hasbeen developed so that photoresist 10 in its cross-linked state remainsin the desired pattern, with the remainder of the photoresist (notcross-linked by the exposure and development) removed from thestructure. Photoresist 10 may either be of the positive or negativetype, with the corresponding photomask or reticle (i.e., positive ornegative) used during exposure.

Typically, the width W of the remaining photoresist element 10 is at ornear the smallest dimension that can be photolithographically patterned.According to current technology, this width W is about 100 nm. However,in this example, the eventual width of the gate electrode to be formedin polysilicon layer 4 is substantially narrower than this 100 nmphotolithographic limit. According to this conventional method,therefore, photoresist element 10 is “trimmed”, or narrowed, by way of atimed isotropic etch. The result of this trim operation is illustratedin FIG. 1 b, with trimmed photoresist element 10′ shown. As evident fromFIG. 1 b, the isotropic nature of this trim etches into both sides ofphotoresist 10, and also reduces its thickness from the top by an amountapproximately one-half of its width reduction. The new width W′ oftrimmed photoresist element 10′ may be on the order of 50 nm.

After the trim operation illustrated in FIG. 1 b, photoresist element10′ is then used to mask the etch of the underlying hardmask layersincluding, in this example, silicon oxynitride layer 8 and silicon-richnitride layer 6. This etch is preferably an anisotropic etch, so thatthe dimension of the resulting hardmask corresponds to that of trimmedphotoresist element 10′. The result of this etch is illustrated in FIG.1 c, with the remaining portions of silicon oxynitride layer 8 andsilicon-rich nitride layer 6 remaining in place over polysilicon layer 4at the location defined by photoresist 10. As evident from FIG. 1 c, thecompletion of this etch can thin silicon oxynitride layer 8.

Polysilicon layer 4 is then anisotropically etched, using the remaininghardmask of silicon oxynitride layer 8 and silicon-rich nitride layer 6to protect the eventual location of the polysilicon gate electrode. Theprotected portion of polysilicon 4 as a transistor gate electrode isillustrated in FIG. 1 d. Some portion of the hardmask, most likely thelower silicon-rich nitride layer 8 but also possibly including siliconoxynitride layer 8, remains over the gate electrode as shown in FIG. 1d; this residue will be removed by a subsequent cleanup or etch, topermit contact to polysilicon 4 (at a wider location than that shown inFIG. 1 d).

This conventional defining of the critical dimension feature of thepolysilicon gate electrode, using the trimming of photoresist, workswell in theory. In practice, however, especially considering theextremely narrow feature sizes and the relatively large film thicknessesfor those small features, this conventional approach has somesignificant limitations.

A first limitation is illustrated in FIG. 1 e, in which post-trimphotoresist element 10″ is illustrated. If the aspect ratio of height(thickness) to width of photoresist element 10″ is too high, such as 3:1or higher, photoresist element 10″ may not be able to structurallysurvive the trim operation. More specifically, stress deformation ofphotoresist element 10″ occurs as a result of the trim, causingphotoresist element 10″ to lean to one side and, in the extreme case, todetach and fall. As a result, deformed photoresist element 10″ cannotproperly protect nor accurately define the hardmask of the underlyingsilicon oxynitride layer 8 and silicon-rich nitride layer 6. Completionof the polysilicon etch process results in unduly narrowed, broken, oreven completely missing polysilicon gate electrode structures, asillustrated in the plan view of FIG. 1 f. As shown in FIG. 1 f,polysilicon gate electrodes 4″ are broken as they extend over moatregion 5 (i.e., the location of source and drain diffusions) betweenwider polysilicon contact structures 4. Obviously, in the case of FIG. 1f, the broken and narrowed polysilicon gate electrodes 4″ are notcapable of operating as transistor gate electrodes to control thecurrent between opposing sides of moat region 5 (i.e., the source anddrain).

Even if the structural integrity of photoresist elements 10″ can bemaintained, this conventional process has other limitations. Asdescribed above, the hard mask layers include both silicon oxynitridelayer 8 and silicon-rich nitride layer 6, of thicknesses that areselected to eliminate optical reflections during exposure, whichconstrains the selection of film thicknesses. But silicon oxynitridelayer 8 is difficult to remove with a wet cleanup after polysiliconetch, Accordingly, in the conventional process of FIGS. 1 a through 1 d,the polysilicon etch must be designed so that silicon oxynitride layer 8is fully consumed by the time that the etch is completed. Thisconstraint on the etch process has been observed to limit theperformance of the etch of polysilicon layer 4 itself, resulting inless-than-optimal defining of the polysilicon gate electrodes and othercritical dimension features.

BRIEF SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide a method ofdefining and forming extremely small physical features in themanufacture of integrated circuits.

It is a further object of this invention to provide such a method inwhich the features are smaller in at least one dimension than theminimum size that can be photolithographically patterned for theprocess.

It is a further object of this invention to provide such a method inwhich the trimming of a masking element results in a structure withsound structural integrity.

It is a further object of this invention to provide such a method inwhich the etch of the layer from which the feature is not constrained byrequiring the removal of a masking layer.

Other objects and advantages of this invention will be apparent to thoseof ordinary skill in the art having reference to the followingspecification together with its drawings.

The present invention may be implemented into a photolithographicprocess of defining a sub-lithographic feature, such as a transistorgate electrode in metal-oxide-semiconductor technology. A hardmasklayer, such as silicon-rich nitride, is formed over the layer from whichthe feature is to be formed (e.g., polysilicon). An anti-reflectivecoating is then formed over the hardmask layer. A photoresist element isthen defined by conventional photolithography, to a feature size that islarger than the eventual desired feature. The anti-reflective layer isetched, so that the pattern of the photoresist element is transferred tothe anti-reflective layer. An isotropic etch is then applied to theanti-reflective layer, trimming its width to the desiredsub-lithographic critical dimension. The hard mask, and in turn theunderlying layer, are then etched to define the sub-lithographicphysical feature.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1 a through 1 d are cross-sectional views illustrating aconventional polysilicon etch process.

FIGS. 1 e and 1 f are cross-sectional and plan views illustratingfailure modes resulting from the conventional process of FIGS. 1 athrough 1 d.

FIGS. 2 a through 2 f are cross-sectional views illustrating a method offorming small physical features in the manufacture of an integratedcircuit according to the preferred embodiment of the invention.

FIG. 3 is a plan view of an example of a structure formed by the methodaccording to the preferred embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described in connection with its preferredembodiment, namely as implemented into a method of forming a transistorgate electrode in a metal-oxide-semiconductor (MOS) integrated circuit,because the invention is believed to be especially beneficial when usedin such an application. However, it is contemplated that this inventioncan also provide similar significant benefits in the formation of otherintegrated circuit features, for integrated circuits of other types anddevice technologies. Accordingly, it is to be understood that thefollowing description is provided by way of example only, and is notintended to limit the true scope of this invention as claimed.

Referring now to FIGS. 2 a through 2 f, a method of defining a smallfeature in an integrated circuit according to the preferred embodimentof the invention, specifically in forming polysilicon gate electrodes inan MOS integrated circuit, will now be described. As mentioned above andas known in the art, the gate electrode in an MOS device is typicallythe smallest feature in the integrated circuit, because the width of thegate electrode defines the electrical channel length of the MOStransistor. The transistor channel length defines important electricalparameters of the integrated circuit, including switching speed anddrive capability, and also effectively defines the density of the activedevices that are to be formed in the integrated circuit. Accordingly, itis a common desire to form the gate electrode of the highest performanceMOS transistors to have as small a width as practicable. According tothis embodiment of the invention, the gate electrode width to be formedis smaller than the smallest dimension that can be patterned withavailable photolithography technology, and as such this dimension can bereferred to as “sub-lithographic”.

FIGS. 2 a through 2 f will illustrate the formation of a single gateelectrode from a layer of polysilicon (i.e., polycrystalline silicon),by way of the photolithography and etching of a number of layers at ornear a semiconducting surface of a body. It will, of course, beunderstood by those skilled in the art having reference to thisspecification that many thousands (indeed millions) of elements will besimultaneously formed along with the formation of the single gateelectrode shown in these Figures, as the integrated circuit containingthis single gate electrode will typically include hundreds of thousandsof such elements, and is formed on a wafer simultaneously with manyother similar integrated circuits. The dimensions of these otherelements may of course vary from that shown in these Figures. The singleexample to which this description pertains is contemplated to beillustrative of a minimum feature size gate electrode formed accordingto this preferred embodiment of the invention.

FIG. 2 a illustrates, in cross-section, a partially formed integratedcircuit including a substrate 22, and an overlying gate dielectric film23. Substrate 22 can be a single-crystal bulk substrate as suggested byFIG. 2 a, or alternatively an epitaxial layer on a bulk substrate, anepitaxial silicon-on-insulator (SOI) film, or another semiconductorlayer into which active devices can be formed at the surface. As knownin the art, particularly for complementary MOS (CMOS) integratedcircuits, p-type and n-type doped regions of the surface of substrate22, referred to as wells or tanks, are typically formed into substrate22; transistor source and drain regions are then later formed into thewells or tanks, as well-known in the art. In addition, isolationstructures are also typically formed at locations of the surface ofsubstrate 22, to define so-called “moat” regions of the surface(typically at the surface of doped wells) at which the transistor sourceand drain regions will be formed. While these and other such structures,disposed below gate dielectric 23, are not shown in FIGS. 2 a through 2f for the sake of clarity, those skilled in the art having reference tothis specification will of course understand that such features will bepresent at and within substrate 22, according to the particular processflow into which the invention is implemented.

Gate dielectric 23 may be a conventional silicon dioxide layer, forexample formed by thermal oxidation of the surface of substrate 22, ormay be formed of another material including nitrided silicon dioxide,other forms of silicon oxynitride, silicon nitride, laminated thin filmsof silicon dioxide and silicon nitride. Other materials used as gatedielectric films include the metal oxides of Ta₂O₅, TiO₂, Y₂O₃, CeO₂,ZrO₂, HfO₂, and Al₂O₃. For such devices as ferroelectric memories,ferroelectric materials such as BST (barium strontium titanate) canserve as gate dielectric 23.

Polysilicon layer 24 is disposed over gate dielectric 23 in thisembodiment of the invention, and is the layer from which the eventualgate electrode will be formed. Of course, other materials mayalternatively be used as the gate electrode material of layer 24, suchmaterials including metals such as tungsten, and metal compounds such astitanium silicide, tungsten silicide, and the like. For purposes of thisdescription, polysilicon is the exemplary material of layer 24.

Hardmask layer 26 overlies polysilicon layer 24, and is of a selectedmaterial of sufficient thickness to protect selected locations ofpolysilicon layer 24 from the polysilicon etch. Preferably, the materialselected for hardmask layer 26 is a material that can be easily removed,for example by way of a wet cleanup, after the etch of polysilicon layer24. A preferred material for hardmask layer 26 is silicon-rich nitride,which, as known in the art, refers to a silicon nitride film in which ahigher than stoichiometric density of silicon is provided (i.e.,Si_(x)N_(y), where the ratio of x:y is greater than 3:4). For example,hardmask layer 26 of silicon-rich nitride may be deposited by chemicalvapor deposition to a thickness of on the order of 50 nm, for apolysilicon layer 24 having a thickness of about 160 nm. Alternatively,it has been discovered that anti-reflective properties may be improvedby using a silicon-rich oxynitride as hardmask layer 26.

According to this preferred embodiment of the invention, bottomanti-reflective coating (BARC) layer 29 is deposited over hardmask layer26. BARC layer 29 is a conventional anti-reflective coating, as known inthe art, to reduce undesired reflections and their effect inphotolithography. The material used for BARC layer 29, and itsthickness, depends on the wavelength of light to be used. Typically,BARC layer 29 is an organic layer designed for the particular wavelengthof light to be used in the photolithography, and having a selectedrefractive index. It is contemplated that those skilled in the arthaving reference to this specification will be readily able to selectthe appropriate material for BARC layer 29 in specific applications.

At the stage of the process illustrated in FIG. 2 a, photoresist element30 is shown as disposed at a selected location of the structure,following its exposure and developing in the photolithography process.Photoresist 30 may be either a negative (cross-linking occurring inunexposed photoresist) or a positive photoresist (cross-linkingoccurring in exposed photoresist), with the photomask or reticlearranged as a positive or negative mask accordingly. The photomask orreticle of course defines the location at which photoresist element 30is to remain after developing. In either case, photoresist element 30remaining after developing as shown in FIG. 2 a consists of cross-linkedphotopolymer.

As shown in FIG. 2 a, photoresist element 30 has a width LW that isdefined by the photolithography process; preferably, this width LW is ator near the minimum critical dimension that can be reliably formed byphotolithography for the particular process technology being used. Forexample, current deep UV (<200 nm wavelength) photolithography canreliably define features as small as about 100 nm. According to thispreferred embodiment of the invention, however, photoresist element 30is not called upon to mask the definition of the entire hardmask layer.As such, its aspect ratio (height H to width LW) need not beparticularly severe. For example, the height (or thickness) H ofphotoresist 30 is preferably less than three times the minimum width W,and preferably defines an aspect ratio that is 2:1 or less.

Following the patterning (exposure and developing) of the photoresistpattern defining photoresist element 30, this pattern is transferred toBARC layer 29 according to the preferred embodiment of the invention. Asshown in FIG. 2 b, this pattern transfer is performed by etching BARClayer 29 with a suitable reagent, preferably anisotropically, usingphotoresist element 30 as a mask. Photoresist element 30 is also thinnedby this BARC etch operation, with the extent of this thinning dependingupon the particular reagent and etch conditions. BARC layer 29 isremoved from other locations of the surface except where masked byphotoresist elements 30.

FIG. 2 c illustrates the trimming of BARC element 29 according to thepreferred embodiment of the invention. As shown in FIG. 2 c, after theremoval of remaining photoresist 30, BARC element 29 is subjected to asubstantially isotropic timed etch using conventional reagents, to trimits width W from the photolithographic minimum to a sub-lithographicwidth. This etch need not be perfectly isotropic and as such may havesome anisotropy (e.g., preferentially vertical); but of course, if theetch has some anisotropy, the etch designer should keep in mind that theprimary purpose of this trim etch is to reduce the width of BARC element29 while still maintaining it sufficiently thick to permit transfer ofthe pattern to underlying layers. The isotropic nature of the trimprocess will also tend to remove photoresist 30 remaining at the surfaceof BARC element 29, and may even thin BARC element 29. To the extentthat photoresist 30 remained after transfer of the pattern to BARCelement 29, this material is preferably left in place during this trimbecause it helps to protect the thickness of BARC element 29 during itstrim and etch, and also because it is difficult to remove photoresist 30without adversely impacting BARC element 29.

The result of this trimming of BARC element 29 is illustrated in FIG. 2d, with trimmed BARC element 29′ having a width SW that is substantiallynarrower than the patterned width W (and with some photoresist 30 stillremaining at the surface of BARC element 29, in this example). Forexample, it is contemplated that BARC element 29 may be trimmed from apatterned width W of about 100 nm to a trimmed width SW of 45 nm orless. The thickness of trimmed BARC element 29′ is preferably sufficientto withstand the subsequent etch of hardmask layer 26, or at least towithstand this subsequent hardmask etch to the extent that the remaininghardmask is thick enough to withstand the subsequent polysilicon etch,as will be described below. For example, a suitable thickness of trimmedBARC element 29′ is on the order of 40 nm, for masking an etch of a 50nm thick silicon-rich nitride film 26.

Hardmask layer 26 is next etched, using trimmed BARC element 29′ as amask. This etch is preferably a substantially anisotropic etch, usingconventional reagents and etch conditions for the etching of thematerial of hardmask layer 26. For example, the etching of hardmasklayer 26 consisting of a 50 nm silicon-rich nitride film can be carriedout by way of a plasma etch using fluorine as the active species, forexample from CHF₃, CF₄, or a mixture of the two; other reagents such asNO may also be used. This etch need not be perfectly anisotropic, butshould be primarily anisotropic so that the critical dimension of thewidth of the resulting hardmask structure is closely controlled whilestill maintaining much of its thickness. To the extent that any portionof trimmed BARC element 29′ remains after this etch, it may be removedby conventional cleanup, such as an O₂ or O₂/N₂ plasma ash, which may beperformed in the same etch chamber used for the etching of hardmasklayer 26 and polysilicon layer 24. The result of the etch of hardmasklayer 26 is illustrated in FIG. 2 e. The width of the remaining hardmaskelement 26′ at the location at which the gate electrode is to be formedcorresponds to the width SW of trimmed BARC element 29′. The thickness,or height, of remaining hardmask element 26′ is preferably sufficient towithstand the subsequent etch of polysilicon layer 24. For example,hardmask element 26′ is preferably about 50 nm thick, for an underlyingpolysilicon layer 24 that is 120 nm thick.

Polysilicon layer 24 is then etched, preferably with a conventionalanisotropic polysilicon etch, using hardmask element 26′ as a mask.Hardmask element 26′ may be thinned by this polysilicon etch, but asmentioned above, it is preferably of sufficient thickness to remain inplace until polysilicon layer 24 is cleared from the unmasked regions ofsubstrate 22. The result of this polysilicon etch is illustrated in FIG.2 f, with polysilicon gate electrode 24′ remaining at the desiredlocation after polysilicon etch. In this example, a thinned portion ofhardmask element 26′ remains in place. But because of its material(e.g., silicon-rich nitride), it is contemplated that this remaininghardmask element 26′ can be easily removed by a wet cleanup, clearingthe surface of polysilicon gate electrode 24′.

The ability to easily remove hardmask element 26′ according to thisembodiment of the invention not only simplifies the process, but in factprovides additional optimization in the design of the polysilicon etch.As mentioned above, the conventional process uses silicon oxynitride ina bilayer hardmask. But because this silicon oxynitride is extremelydifficult to remove by a post-etch cleanup, the polysilicon etch in thisconventional process is constrained to ensure that the siliconoxynitride top layer of the hardmask is completely consumed in thepolysilicon etch. This is further constrained by the thickness of thesilicon oxynitride being selected for anti-reflective propertiesrelative to the underlying silicon-rich nitride. In contrast, there isno such constraint according to the method of this preferred embodimentof the invention. The duration, reagents, and etch conditions for theetch of polysilicon layer 24 can be optimized for this polysilicon etch,and need not be concerned with the removal of difficult materials suchas silicon oxynitride. This additional degree of freedom for thepolysilicon etch will result in ensuring that the dimensions of thecritical gate electrode features can be closely and reliably controlled,along with avoiding filaments at steps in the polysilicon and the like.This additional degree of freedom can also be useful in closelycontrolling the profile of the resulting gate electrode defined by thispolysilicon etch.

FIG. 3 illustrates, in plan view, a pair of typical transistors formedat a surface of substrate 22 according to this embodiment of theinvention. Moat regions 25 are disposed at selected locations of thesurface of substrate 22, specifically at locations not otherwise coveredby isolation oxide 27 as shown. A single polysilicon structure 24including gate electrodes 24 extends over moat regions 25, withrelatively wide features at portions overlying isolation oxide 27. Gateelectrodes 24′, formed according to the process described above relativeto FIGS. 2 a through 2 f, extend between these wider features, acrossmoat regions 25. As shown in FIG. 3, gate electrodes 24′ are unitarywith good integrity along their lengths, despite being formed to anextremely narrow sub-lithographic width. This integrity is in starkcontrast to the failures described above that result from theconventional process of FIG. 1 a through 1 d.

As is well-known in the art, processes subsequent to the formation ofgate electrodes 24′ according to this preferred embodiment of theinvention can now be performed to complete the fabrication oftransistors and other devices in the integrated circuit. Thesesubsequent processes include the ion implantation and anneals forforming source and drain diffusion regions on either side of gateelectrodes 24′ in moat regions 25 of FIG. 3, in the conventionalself-aligned manner. Moat regions 25 and polysilicon structure 25 may bethen silicide-clad in the conventional manner, as known in the art.Additional conductor levels of polysilicon or metal, separated byinterlevel dielectric layers, are then typically added as known in theart. Upon completion of the fabrication of the integrated circuit,electrical test and packaging of the integrated circuits is then carriedout, as well known in the art. The specific materials, layout, number oflevels, and other attributes of these subsequent processes will, ofcourse, depend upon the particular integrated circuit being fabricatedand the technology used for such fabrication.

This invention provides important benefits in the manufacture ofintegrated circuits, specifically in the formation of physical featuresof so-called critical dimension. According to this invention, minimumdimension features, such as MOS transistor gate electrodes, can bereliably formed to dimensions that are less than that achievable byconventional photolithography. More specifically, the masking structuresused to form these features have good structural integrity, avoiding acommon limitation of conventional patterned masking materials forforming these structures. In addition, the masking materials can beselected to provide low reflections in photolithography, while beingeasily removed by post-etch cleanups; as a result, the etch of the gateelectrode layer can be optimized for its own properties, without beingconstrained by the removal of masking material as in conventionalprocesses.

It is contemplated that various alternatives to the preferred embodimentof the invention will be apparent to those skilled in the art havingreference to this specification. Of course, the particular thicknessesand composition of the layers can vary according to the particularprocess implementation. For example, the thickness of silicon-richnitride layer 26 can vary in thickness, and in its composition (i.e.,the concentration of silicon in the film), to obtain the desired opticalproperties for particular thicknesses of polysilicon layer 24 and theother layers in the gate stack structure. By way of further example, ithas been observed, in connection with this invention, that the indicesof absorption and refraction of a silicon-rich nitride film vary withthe silicon concentration in the film. This invention thus providesanother degree of freedom in the selection of this silicon concentrationfor optimal optical properties, as well as in selecting the particularfilm thicknesses, because etch of the hardmask layer is not constrainedby also having to simultaneously remove an overlying silicon oxynitridefilm, as is necessary in conventional processes. Other alternativeapproaches contemplated by this invention include the including ofadditional layers in the gate stack, such as a silicon dioxide layerunderlying the silicon-rich nitride hardmask layer that can be includedto further adjust and optimize the optical properties of the stack.

While the present invention has been described according to itspreferred embodiments, it is of course contemplated that modificationsof, and alternatives to, these embodiments, such modifications andalternatives obtaining the advantages and benefits of this invention,will be apparent to those of ordinary skill in the art having referenceto this specification and its drawings. It is contemplated that suchmodifications and alternatives are within the scope of this invention assubsequently claimed herein.

1. A method of fabricating a feature in an integrated circuit structure,comprising: forming a feature layer near a semiconducting surface of asubstrate; forming a hardmask layer over the feature layer; forming ananti-reflective coating over the hardmask layer; patterning photoresistover the anti-reflective coating, to expose selected locations of theanti-reflective coating; removing the exposed portions of theanti-reflective coating; then trimming remaining portions of theanti-reflective coating to reduce their width; etching the hardmasklayer, using trimmed remaining portions of the anti-reflective coatingas a mask, to expose selected locations of the feature layer; etchingthe exposed locations of the feature layer, using remaining portions ofthe hardmask layer as a mask; and removing the remaining portions of thehardmask layer.
 2. The method of claim 1, further comprising: after thestep of etching the hardmask layer, removing remaining portions of theanti-reflective coating.
 3. The method of claim 1, wherein theanti-reflective coating comprises an organic BARC layer.
 4. The methodof claim 1, wherein the hardmask layer comprises silicon-rich nitride.5. The method of claim 1, wherein the step of removing remainingportions of the hardmask layer comprises performing a wet cleanup. 6.The method of claim 1, wherein the hardmask layer comprises silicon-richoxynitride.
 7. The method of claim 1, wherein the feature layercomprises polycrystalline silicon.
 8. The method of claim 1, wherein thetrimming step comprises: etching the anti-reflective layer substantiallyisotropically, for a selected time.
 9. The method of claim 8, furthercomprising: after the step of removing exposed portions of theanti-reflective coating and before the isotropically etching step,removing remaining photoresist.
 10. A method of forming a transistor foran integrated circuit, comprising: forming a gate dielectric layer at asemiconducting surface of a substrate; forming a gate layer over thegate dielectric layer; forming a hardmask layer over the gate layer;forming an anti-reflective coating over the hardmask layer; patterningphotoresist over the anti-reflective coating, to expose selectedlocations of the anti-reflective coating; removing the exposed portionsof the anti-reflective coating; then trimming remaining portions of theanti-reflective coating to reduce their width; etching the hardmasklayer, using trimmed remaining portions of the anti-reflective coatingas a mask, to expose selected locations of the gate layer; etching theexposed locations of the gate layer, using remaining portions of thehardmask layer as a mask, to define a gate electrode; and removing theremaining portions of the hardmask layer.
 11. The method of claim 10,further comprising: forming source and drain regions in thesemiconducting surface adjacent the gate electrode.
 12. The method ofclaim 10, further comprising: after the step of etching the hardmasklayer, removing remaining portions of the anti-reflective coating. 13.The method of claim 10, wherein the anti-reflective coating comprises anorganic BARC layer.
 14. The method of claim 10, wherein the hardmasklayer comprises silicon-rich nitride.
 15. The method of claim 10,wherein the step of removing remaining portions of the hardmask layercomprises performing a wet cleanup.
 16. The method of claim 10, whereinthe hardmask layer comprises silicon-rich oxynitride.
 17. The method ofclaim 10, wherein the gate layer comprises polycrystalline silicon. 18.The method of claim 10, wherein the trimming step comprises:isotropically etching the anti-reflective layer for a selected time. 19.The method of claim 18, further comprising: after the step of removingexposed portions of the anti-reflective coating and before theisotropically etching step, removing remaining photoresist.